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  • Analysis of a Parasitic Diode Triggered ESD Protection Circuit for 12 V Applications
  • Bo-Bae Song, Byoung-seok Lee, Yil-Suk Yang, and Yong-Seo Koo
  • Received Jan, 18. 2017    Accepted Feb, 23. 2017    Published online March 31, 2017
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Abstract :
In this paper, an electrostatic discharge (ESD) protection circuit is designed for a 12 V power clamp by using a parasitic diode triggered silicon controlled rectifier (SCR). The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding n+/p+ floating regions; moreover, segmented technology improves the holding voltage (Vh). The proposed ESD protection circuit was fabricated using a 0.18 µm Bipolar-CMOS-DMOS (BCD) process with a width of 100 µm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse (TLP) measurements and an ESD pulse generator (ESS-6008). The electrical characteristics of the proposed circuit were analyzed at high temperature (300 K to 500 K) to verify the ESD robustness. Further, Vt of the proposed ESD protection circuit increased from 14 V to 27.8 V and Vh increased from 5.3 V to 13.6 V. The proposed circuit also exhibited good robustness for a human body model (HBM) at 7.4 kV and a machine model (MM) at 450 V.

Keyword :
ESD, SCR, Diode, Latch-up, trigger voltage, holding voltage, robustness

DOI :
http://dx.doi.org/10.4218/etrij.17.0117.0026

Cite this :
Bo-Bae Song, Byoung-seok Lee, Yil-Suk Yang, and Yong-Seo Koo, "Analysis of a Parasitic Diode Triggered ESD Protection Circuit for 12 V Applications," to be published in ETRI Journal, 2017.
http://dx.doi.org/10.4218/etrij.17.0117.0026

References :