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  • Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials
  • Sudha Ellison Mathe and Lakshmi Boppana
  • Received Nov, 07. 2016    Accepted Mar, 28. 2017    Published online May 31, 2017
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Abstract :
Multiplication in Finite Fields is used in many applications, especially in cryptography. It is a basic and most compute intensive operation among all the operations. Several systolic multipliers are proposed in the literature which offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. Hardware complexity and delay of the proposed multiplier is estimated and comparison with the corresponding multipliers available in the literature is presented. The proposed multiplier achieves up to 20% reduction in hardware complexity when compared to the best multiplier among existing systolic multipliers for m = 163. The synthesis results of application specific integrated circuit (ASIC) and field-programmable gate array (FPGA) implementations of the proposed multiplier are also presented. It is inferred from the synthesis results that the proposed multiplier achieves low power consumption & area cost when compared to the best of the corresponding multipliers.

Keyword :
Finite field, Cryptography, Systolic, Polynomial basis, Application Specific Integrated Circuit, Field Programmable Gate Arrays.

DOI :
http://dx.doi.org/10.4218/etrij.17.0116.0770

Cite this :
Sudha Ellison Mathe and Lakshmi Boppana, "Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials," to be published in ETRI Journal, 2017.
http://dx.doi.org/10.4218/etrij.17.0116.0770

References :