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Article  <  Archive  <  Home
FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation
José María Hinojo, Clara Lujan-Martinez, Antonio Torralba, and Jaime Ramirez-Angulo
vol. 39, no. 3, June. 2017, pp. 373-382.
http://dx.doi.org/10.4218/etrij.17.0116.0766
Keywords : Low drop-out (LDO), Voltage regulator, Flipped voltage follower (FVF).

This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/news/dataView.do?dataIdx=97).
Manuscript received  Oct. 27, 2016;   revised  Mar. 06, 2017;   accepted  Mar. 08, 2017.  
  • Abstract
    • Abstract

      A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 µV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 µs. The total current consumption is 17.88 µA (for a 0.9 V supply voltage).
  • Authors
    • Authors

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_a001.jpg

      Corresponding Author jhinojo@gie.us.es

      José María Hinojo received his PhD degree from the University of Seville, Spain, in 2016. Since 2007, he has been with the Department of Electronic Engineering, University of Seville, where he is currently a researcher. His research interests are in power management and analog circuits.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_a002.jpg

      cilujan@gie.us.es

      Clara Luján-Martínez received her telecommunication engineering and PhD degrees from the University of Seville, Spain, in 2007 and 2009, respectively. Since 2007, she has been with the Department of Electronic Engineering, University of Seville, where she is currently working as a postdoctoral researcher. She was an invited researcher at the Imperial College of London, UK in 2008 and at NXP Semiconductors Eindhoven, Netherlands in 2011. Her main research interests are in low-power low-voltage analog and mixed-signal microelectronics.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_a003.jpg

      taorralba@gie.us.es

      Antonio Torralba (M’89, SM’02) received his industrial engineering (MSc in electrical engineering) and PhD degrees from the University of Seville, Spain, in 1983 and 1985, respectively. Since 1983, he has been with the Department of Electronics Engineering, University of Seville, where he is a professor and head of department, leading a research group on mixed signal design. He was a visiting researcher at the Klipsch School of Electrical Engineering, New Mexico State University, Las Cruces, USA, in 1999, and at the Department of Electrical Engineering, Texas A&M University, College Station, USA, in 2004. Prof. Torralba is the co-author of 90 papers in international journals. His research interests include low-power low-voltage analog and mixed-signal microelectronics.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_a004.jpg

      jairamir@nmsu.edu

      Jaime Ramírez-Angulo (F’00) received his degree in communications and electronic engineering and the MSEE degree from the National Polytechnic Institute, Mexico City, and the Dr.-Ing. degree from the University of Stuttgart, Germany, in 1974, 1976, and 1982, respectively. He is currently a Klipsch Distinguished Professor and director of the Mixed-Signal VLSI Lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, USA. He was a professor at the National Institute for Astrophysics Optics and Electronics (INAOE) and at Texas A&M University, Colleage Station, USA. His research is related to various aspects of design.

  • Full Text
    • I. Introduction

      The system-on-chip (SoC) paradigm, motivated by a high demand in the industrial and multimedia markets for portable and battery-powered devices, has raised significant challenges in analog design. SoCs integrate a large number of electronic components into a single chip, thus reducing the number of interconnections, total power consumption, silicon area, and consequently, the total cost of the system. This approach implies that digital, analog, and RF circuits must coexist in the same die, although they have different supply requirements (concerning noise, voltage, and maximum current). Therefore, powering the different blocks of a SoC from a single battery requires the conversion and adaption of the supply signal.

      This makes power management one of the major issues in SoC design. Internally compensated low drop-out (LDO) voltage regulators have proven to be essential blocks because they generate an accurate regulated voltage with high efficiency under large variations in load current and input voltage without the addition of external components.

      Several techniques [1][7] have been proposed to improve the transient response of internally compensated LDO regulators at the cost of increasing their quiescent power consumption or degrading the rest of their performance (load and line regulations and the power supply ripple rejection ratio [PSRR]). Many of the techniques in these references use the classical LDO topology. However, Carvajal and others [8] and Ramirez-Angulo and others [9] chose the flipped voltage follower (FVF) cell as an alternative topology. This cell, shown in Fig. 1(a), offers simplicity in addition to low output impedance and good performance acting as a current buffer, which makes it a highly efficient LDO regulator. In addition, according to [10], FVF-based LDOs are more power efficient than the classical LDO topology for similar transient performance. However, despite this enhancement in efficiency, the transient response of FVF-based LDOs still needs to be improved to reduce voltage spikes at the output node under the constraint of low quiescent power consumption.

      Currently, many schemes to improve the load regulation and transient response of this structure can be found in the literature [11][19]. In [11], Man and others take advantage of FVF properties to implement a simple LDO regulator for different values of the output capacitor, equivalent series resistance, and load current. However, this provides a low open-loop gain, and therefore, a high quiescent power consumption is necessary to achieve the required gain to provide a reasonable load regulation. Blakiewicz and others [12] show some improvement by cascading the IBIAS,A1 current source with an additional transistor in order to obtain a higher equivalent resistance at the “GATE node,” as shown in Fig. 1(a). This arrangement increases the open-loop gain. In addition, a capacitive coupling of VOUT to the source of the cascode transistor is introduced to increase the current that discharges the parasitic capacitance at the gate of the pass transistor MPASS (CPASS). However, a higher minimum input voltage and a large on-chip capacitor are required to properly operate this LDO regulator.

      Further improvements regarding the open-loop gain have been achieved using a cascode flipped voltage follower (CAFVF) cell [13][16]. As shown in Fig. 1(b), the CAFVF cell consists of two common-gate amplifiers implemented as M2 and M3. In [13], a regulator with fast load regulation is proposed, where the output node is driven by multiple in-parallel CAFVF-based buffers. In order to maintain output voltage peaks under 10% of their nominal value for a 0 mA to 100 mA load current change, a large on-chip decoupling capacitor is required, which leads to a large silicon area. In [14] and [15], the transient response is improved by using RC couplings, which sense the output variations and change the IBIAS,B1 and IBIAS,B2 values accordingly. Nevertheless, these RC couplings do not react to line voltage variations, which could produce large voltage spikes at the output. An alternative way to implement a dynamic biasing circuit is presented in [16], where RC coupling is substituted with a digital circuit to increase the charging/discharging current of CPASS. This technique speeds up the transient response, allowing a reduction in the area consumed by the passive components required for load voltage regulation. However, no information is provided in [16] regarding the performance of that structure under large line voltage variations.

      Fig. 1.

      (a) FVF cell configuration and (b) CAFVF cell.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f001.jpg

      Another technique proposed to improve the transient response of FVF-based LDOs is presented in [17][19]. A noninverting gain stage is inserted to drive the gate of the pass transistor, enhancing the slew rate (SR) and the open-loop gain. In [17], a gain-enhanced CAFVF-based LDO is presented. However, despite the increase in the open-loop gain, the circuit is only stable for a minimum output current of 3 mA, and the line transient response has a long settling time. Tan and others [18] additionally use a dual-summed Miller compensation to stabilize the regulator for a minimum load current of 0 mA. In [19], a buffered FVF with a triple-path input error amplifier (EA) is used to improve the PSRR. However, the maximum load current is limited to 10 mA, and a high quiescent consumption is required. From [17][19], it can be concluded that inserting a gain stage in the feedback loop of an FVF enhances the load regulation, but a careful study of the frequency response is required because the classical Miller compensation is not applicable.

      In this paper, a low-power LDO regulator based on the CAFVF is proposed. This regulator exhibits a good transient response for extreme load and line variations.

      The rest of this paper is organized as follows: Section II describes the structure and principle of operation of the proposed LDO regulator. In Section III, frequency response and stability issues are discussed. The measurements of the proposed LDO regulator are provided in Section IV. Finally, in Section V, some conclusions are drawn.

      II. Structure and Principle of Operation

      The core of the proposed LDO regulator is the CAFVF cell, as shown in Fig. 1(b). In particular, MPASS is the pass transistor, which is responsible for providing the current to the load. In the same figure, M2 is a common gate amplifier acting as an EA: it compares the output of the LDO with a reference voltage VSG_M2, which is connected to its gate (1), and couples the variations of VOUT, amplified by its gain, to “node A,” as shown in Fig. 1(b). Finally, M3 is a second common gate amplifier, which increases the open-loop gain. In this structure, CPASS is charged or discharged by adjusting the gate voltage of MPASS, the “GATE node” in Fig. 1(b), to the required value that sets VOUT to its nominal value. This is achieved owing to the folded cascode amplifier formed by M2, M3, and the current sources IBIAS,B1 (the active load) and IBIAS,B2 (the current source used for folding).

      V REF = V OUT V SG, M 2 .
      (1)

      The CAFVF structure has its transient response limited by IBIAS,B1 and IBIAS,B2. In order to tackle this limitation, a thorough study on the transient response of an LDO regulator is needed. Indeed, it can be demonstrated that the SR at the gate of the pass transistor limits the settling time [20]. This is because the EA is responsible for charging and discharging CPASS, and consequently, for decreasing or increasing the pass transistor gate voltage. In conclusion, if its SR is not high enough, the error at the output voltage will persist for a long settling time. Figure 2 depicts an example of such a situation for a case where the load current abruptly changes from ILOAD,min to ILOAD,max.

      Fig. 2.

      Example of signal evolution for ILOAD variation for internally compensated Low Dropout voltage regulator under Slew-Rate constraints.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f002.jpg

      1. Proposed Architecture with Fast Settling Schemes

      In order to compensate for the poor settling time of the CAFVF under low-power constraints, this paper proposes an alternative version of this cell that enhances the transient response for both load and line variations without negative effects on the quiescent power consumption or the stability of the circuit. Figure 3 depicts the complete scheme of the proposed LDO, where the gain of the regulation loop is increased by means of the gain-boosting amplifier A0 [21] without degrading the speed of the circuit. In order to avoid instability, this auxiliary amplifier was designed according to the method explained in [22]. A compensation capacitor for A0 is not required because the parasitic gate-source capacitance is large enough and is approximately constant.

      Fig. 3.

      Structure of proposed LDO: Circuit core showing blocks that improve settling time and limit overshoot. Detailed view of implementation of amplifiers A0, A1 and A2 is also included.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f003.jpg

      In addition, the line and load transient responses were improved by dynamically increasing the currents responsible for charging/discharging CPASS. In particular, IBIAS,B1 was replaced by a charge-fast settling path (C-FSP) that is formed by a dynamic current source that increases the charging current of CPASS when the input or output voltage increases. This block was implemented by transistors M7 to M14 and the gain-boosting amplifier A1. For A1, the design considerations were similar to those used for A0. As mentioned in Section II, when the voltage VIN rises, VOUT instantaneously tends to grow. Thus, VGATE must be rapidly increased to recover the nominal value of the output voltage. To this end, a high transient current IBIAS,B1 is provided by means of RC coupling (R1C1) to increase the positive SR (SR+) at the gate of MPASS. Moreover, the output voltage is also coupled (through C2) to magnify this effect because magnitudes VIN and VOUT tend to exhibit similar behavior.

      A symmetrical discharge-fast settling path (D-FSP) was included to dynamically increase the discharging current of CPASS when the input or output voltages decrease. Note that, in this case, an additional inverting amplifier (A2) is required. This is implemented with a simple, low-power differential pair.

      In order to reduce static power consumption, A2 is biased in the subthreshold region and M38 is biased in the edge from saturation to the linear region. When VIN or VOUT decreases, the current through transistor M38 rapidly increases owing to a change in its operating region from saturation to the linear region, as described in [23]. This effect, as well as the effect of the multiplying factor K = 1:5.5 of the current mirror (which is composed of M37 through M38 [W/L = 20 μm/0.12 μm] and M39 through M40 [W/L = 110 μm/0.12 μm]), generate a high transient current in the VGATE branch, and consequently produce a large negative SR (SR−) at the gate of MPASS. Figures 4 and 5 depict the large transient charging and discharging currents that enhance the SR. In these figures, IAB = IBIAS,B1IB, and IB is the total current that flows through M3 and M40.

      Fig. 4.

      Dynamic behavior of currents (Fig. 3) when ILOAD changes in a square wave between its minimum (0.1 mA) and maximum (100 mA) with rising and falling time of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f004.jpg
      Fig. 5.

      Dynamic behavior of currents (Fig. 3) when VIN changes in a square wave between its minimum (0.9 V) and maximum (1.2 V) with rising and falling time of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f005.jpg

      Finally, in order to reduce the overshoot when the load current is switched from a heavy load to a light load, capacitor C3, resistor R2, and transistor M4 are added. Note that under steady state conditions, M4 is in the cut-off region, but when ILOAD decreases, R2 and C3 (Table 1) sense the voltage spikes from VA (Fig. 3) and couple them to the gate of M4. This momentarily increases the discharging current. As a consequence, the magnitude of the overshoot is reduced, and the transient response is enhanced.

      Table 1.

      Selected values used for RC couplings.

      DeviceValueDeviceValue
      R1100 (kΩ)C21.25 (pF)
      R2335 (kΩ)C35 (pF)
      R3100 (kΩ)C40.125 (pF)
      C10.125 (kΩ)C51.25 (pF)

      In order to achieve an effective overshoot reduction, transistor M4 is sized to sink enough current and maintain the overshoot under 10% of the nominal output voltage value without degrading the total area of the proposed LDO. According to this trade-off, the aspect ratio of transistor M4 is 300 μm/0.06 μm.

      Note that the resistor values (R1 to R3) were chosen to move the RC coupling effects toward a high frequency. For these values of the resistors, capacitors C1 to C5 are calculated to achieve the appropriate increment of VGATE (2) in order to provide the required current. Table 1 lists the values of these components.

      C = R Δ t ln [ 1 Δ V GATE Δ t Δ V IN ] .
      (2)

      Biasing voltages are generated by the circuit shown in Fig. 6. Each branch is formed by transistors in a single-diode connection (MP1,VCP and MP2,VCP or MN1,CN and MN2,CN for PMOS and NMOS versions, respectively), and by a cascode current source (MBP1 or MBN1). Specifically, the aspect ratios of MP1,VCP or MN1,VCN, which operate in the triode region, are chosen to be lower than those of MP2,VCP or MN2,VCN in order to create the required gate voltage to supply the cascode transistor. VBIAS in Fig. 3 is an external source. The current consumption of the biasing circuitry is 3.6 μA, as IBIASING is chosen to be 100 nA. Table 2 lists the sizes of the transistors and the current ratios for the circuit in Fig. 6.

      Fig. 6.

      Cascode and VBIAS voltage biasing circuits.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f006.jpg
      Table 2.

      Multiplying factors and aspect ratios for transistors in biasing circuit.

      TransistorAspect ratio (width (μm)/length (μm))Current ratioValue
      MN1,VCN0.14/1.39M04
      MP1,VCP0.12/1.49N04
      MBN1MBN20.14/0.12N/AN/A
      MBP1MBP20.30/0.12N/AN/A

      III. Stability Analysis

      In this section, the stability analysis of the proposed LDO is studied. The major concern for stability in the case of internally compensated LDOs is in their load current variations. Small-signal parameters are significantly modified, and this affects the locations of poles and zeros. This is not the case for line voltage variations.

      A simplified small-signal model of the proposed structure is depicted in Fig. 7, where gm,i and ro,i are the transconductance and output resistance of transistor Mi, respectively. Note that the poles and zeros derived from the RC couplings are neglected because they are located at a very high frequency.

      Fig. 7.

      Small-signal model of proposed LDO.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f007.jpg

      H ( s ) = A OL 1 + a 1 s + a 2 s 2 + a 3 s 3 + a 4 s 4 + a 5 s 5 + a 6 s 6 1 + b 1 s + b 2 s 2 + b 3 s 3 + b 4 s 4 + b 5 s 5 + b 6 s 6 + b 7 s 7 ,
      (3)

      A OL = g m 2 g mp R L || r op R out,D FSP ,
      (4)

      ω p 1 = 1 ( g mp R out,D FSP R L || r op ) [ C M 1 + C M 2 + C gdp ] .
      (5)

      Concerning the transfer function in (3), the DC gain is approached by (4) and the dominant pole is given by (5). Rout,D-FSP is the output impedance of the D-FSP block, and the nondominant pole is fixed by the output resistance and CLOAD. Approximate values for the transfer function (TF) coefficients are given in (7) to (13) and (16) to (25). A reduction in the load current, ILOAD, will bring the nondominant pole closer to the Unity Gain Frequency (UGF), thus degrading the stability. This behavior is represented by the pole-zero map in Fig. 8. For the sake of clarity, only poles and zeros below 100 MHz are included in the figure. Nested Miller compensation (NMC), consisting of components RM1, CM1, RM2, and CM2, was used to achieve a proper phase margin in an output current range of 0.1 mA to 100 mA. This resulted in RM1 = 1 kΩ, CM1 = 5 pF, RM2 = 10 kΩ, and CM2 = 8 pF.

      Fig. 8.

      Simplified pole-zero map for poles and zeros below 100 MHz.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f008.jpg

      Post-layout simulations of the open-loop gain are shown in Fig. 9 at different load conditions (100 μA, 1 mA, 10 mA, and 100 mA). Table 3 summarizes the simulated post-layout gain and phase margin values. In every case, the load capacitor is 100 pF, which is the worst-case scenario. Note that the proposed LDO is stable across the entire range of operation.

      Fig. 9.

      Simulated post-layout open-loop gain of circuit in Fig. 3(a).

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f009.jpg
      Table 3.

      Simulated post-layout gain and phase margin values for different load conditions.

      ILOAD (mA)Gain (dB)PM (°)ILOAD (mA)Gain (dB)PM (°)
      10051.30132.0156.65115.7
      1057.24122.20.154.38107.2

      IV. Experimental Results

      The proposed circuit was designed and implemented using standard 65-nm CMOS technology. Figure 10 shows a chip microphotograph next to the layout of the circuit, where the area denoted by the number 1 indicates the pass transistor MPASS, and number 2 is the core of the circuit and the fast settling blocks. Number 3 corresponds to the overshoot limiter implemented by M4, R2, and C3, whereas number 4 is associated with the biasing circuit. The total area is 340.8 μm × 135.5 μm. The core of the circuit occupies an area of 90.2 μm × 135.5 μm.

      Fig. 10.

      LDO layout superimposed on chip microphotograph.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f010.jpg

      The LDO was designed to drive a maximum load current of 100 mA with a variable ILOAD in the range 0 pF to 100 pF.

      a 1 = R 3 C 3 ,
      (6)

      a 2 = R 3 C 3 [ R M 2   C M 2 + R M 1 C M 1 ] ,
      (7)

      a 3 = R 3 R M 2 C 3 C M 2 [ R M 1 C M 1 + R gGB,NMOS C gg,NMOS A 0 + R gGB,PMOS C gg,PMOS A 1 ] ,
      (8)

      a 4 = α [ 1 g m 3 + R M 2 ] ,
      (9)

      α = R M 1 R 3 R GB,NMOS C M 1 C M 2 C 3 C gg,NMOS A 0 ,
      (10)

      a 5 = β [ 1 g m , 3 + R M 2 g m , 3 r o , 3 + R M 2 + 1 g m , 8 g m , 3 r o , 7 ] ,
      (11)

      β = α R GB,PMOS C gg,PMOS A 1 ,
      (12)

      a 6 = β C gdp [ R M 2 g mp + 1 g mp g m , 3 + 1 g m , 8 g m , 3 [ 1 r o , 8 + 1 r o , 7 ] ] .
      (13)

      Experimental results are shown in Figs. 11 and 12 for the worst-case scenario of CLOAD, that is, 100 pF. Figure 11 depicts the line transient response for VOUT = 0.7 V and ILOAD = 100 mA, with VIN changing from 0.9 V to 1.2 V and vice versa. In both cases, the rise and fall times of VIN are 1 μs. Under these conditions, the output voltage shows an overshoot of 45.2 mV and an undershoot of −61.4 mV. In addition, the worst settling time, which was calculated as the time to reach 1% of steady-state VOUT, is 5.17 μs. Figure 12 shows the load transient response for rise and fall times of 1 μs when VIN = 0.9 V and the load current changes from 0.1 mA to 100 mA and vice versa. The voltage VOUT shows a maximum variation of +75.9 mV / −67.5 mV with respect to the nominal voltage VOUT = 0.7 V. Under these conditions, the worst settling time is 4.64 μs. From Figs. 11 and 12, it can be deduced that the proposed architecture exhibits a fast transient response for changes in both VIN and ILOAD.

      Fig. 11.

      Measured line response with CL = 100 pF and ILOAD = 100 mA. (a) From 0.9 V to 1.2 V; and (b) from 1.2 V to 0.9 V with rise and fall times of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f011.jpg
      Fig. 12.

      Measured load transient response with CL = 100 pF and VIN = 0.9 V. (a) From 100 mA to 0.1 mA; and (b) from 0.1 mA to 100 mA with rise and fall times of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f012.jpg

      Table 4 compares the performances of the proposed implementation to other reported LDO regulators. The results presented here correspond to the worst-case scenario (according to the respective authors), measured when ILOAD and VIN are changed between their extreme values.

      Table 4.

      Comparison of recently published LDO regulators.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_t001.jpg

      a Simulation results

      b Estimated using the maximum value of quiescent consumption

      F O M = T r I q I LOAD,max ,
      (14)

      T r = C OUT Δ V OUT I LOAD,max ,
      (15)

      In order to compare different LDO regulators, the figure of merit (FOM) of (14), used in [13], is adopted here. Tr is the response time, and it is defined in (15).

      Based on (14) and (15), the smaller the regulator FOM, the better its performance. Only the regulator of [17] outperforms the present structure. However, the classical FOM does not take into account the rise and fall times of the stimulus used to measure the transient response. Based on this observation, the regulator proposed in [17] has a poor line transient response because it cannot handle rise and fall times shorter than 10 μs of the input voltage. This is not the case for the proposed LDO, which is able to handle rise and fall times of 1 μs. In addition, a minimum load current of 1.5 mA is required for [17] to ensure stability when COUT and VIN take their maximum and minimum values, respectively. This current is increased to 3 mA when COUT and VIN are at their maximum values. On the other hand, the structure proposed in this work remains stable for a minimum current of 0.1 mA, regardless of the COUT and VIN values. A similar reasoning applies to [15], where the experimental results demonstrate that the circuit cannot handle line transient variations of VIN faster than 100 μs. Moreover, it requires almost 50% more power consumption than the LDO presented in this paper. Figure 13 shows a graphical comparison of recently published LDOs.

      Fig. 13.

      Graphical comparison of recently published LDO regulators according to FOM proposed in [13].

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f013.jpg

      γ = g mp R out,D FSP R L || r op ,
      (16)

      b 1 = γ [ C M 1 + C M 2 + C gdp ] ,
      (17)

      b 2 = γ R 3 C 3 [ C M 1 [ 1 + 1 g mp R L || r op ] + C M 2 + C gdp ] ,
      (18)

      δ = γ R 3 R M 2 C 3 C M 2 ,
      (19)

      b 3 = δ [ C M 1 + C gdp + R GB,NMOS C gg,NMOS A 0 R M 2 + C M 1 g mp r op ] ,
      (20)

      b 4 = δ [ [ R GB,NMOS C gg,NMOS [ C M 1 A 0 [ 1 + 1 g m , 3 r o , 3 ] + C M 1 + C gdp   g m , 3 R M 2 A 0 ] + R GB,PMOS C M 1 C gg,PMOS A 1 ] + C M 1 g mp [ C LOAD + R GB,NMOS C gb,NMOS g m , 3 r op R M 2 K 1 ] ]   ,
      (21)

      ϵ = δ R GB,NMOS C M 1 C gg,NMOS K 1 ,
      (22)

      b 5 = ϵ [ R GB,PMOS [ C gg,PMOS A 1 [ 1 + 1 g m , 3 R M 2 ] + C L g mp [ 1 + 1 g m , 3 R M 2 + C gsp g m , 3 C M 1 ] ] + R M 1 C gdp g m , 3 R M 2 ] ,
      (23)

      b 6 = ϵ R GB,PMOS C gg,PMOS A 1 R M 2 [ R M 2 + I g m ,3 + 1 g m p g m , 3 [ C L [ C M 1 + C gsp ] + R M 1 C M 1 C gsp R L || r op   ] ]          + ϵ 1 g mp R M 2 [ R M 1 R M 2 C gsp C gg,PMOS g m , 8 r o , 8 A 1 + R M 1 C L C gsp g m , 3 + R GB,PMOS R M 2 C L C gg,PMOS A 1 ] ,
      (24)

      b 7 = ϵ R GB,PMOS R M 1 C L C gg,PMOS A 1 g mp R M 2   [ C gsp + C gdp g m , 3 + R M 2 [ C gsp + C gdp ] + C gsp g m , 3 g m , 8 r o , 7 ] .
      (25)

      V. Conclusions

      This paper proposes a new LDO regulator based on the CAFVF cell. The structure, designed with standard 65-nm CMOS technology, uses a gain-boosting technique, adaptive biasing, and fast settling paths to increase the regulation loop gain and rapidly charge/discharge the parasitic capacitance of the pass transistor gate. This leads to a fast transient response with a low power quiescent consumption. An analysis of the small-signal behavior of the proposed structure, which uses NMC, demonstrates its adequate stability in the worst case. Experimental results show small voltage spikes and short settling time for large line and load transient variations, even when the rising and falling times decrease to 1 μs. Finally, the proposed LDO regulator is shown to be a state-of-the-art device.

      Footnotes

      José María Hinojo (corresponding author, jhinojo@gie.us.es), Clara Luján-Martínez (cilujan@gie.us.es), and Antonio Torralba (taorralba@gie.us.es) are with the Department of Electronic Engineering, Universidad de Sevilla, Spain.

      Jaime Ramírez-Angulo (jairamir@nmsu.edu) is with the Department of Electrical and Computer Engineering, New Mexico State University, Las Cruces, USA.

      This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project TEC2015-71072-C3-3-R, and the Andalousian “Consejería de Economía, Innovación y Ciencia” under the project P12-TIC-1862.

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      Y. Kim and S.-S. Lee, “A Capacitorless LDO Regulator with Fast Feedback Technique and Low-Quiescent Current Error Amplifier,” IEEE Trans. Circuits Syst. II: Exp. Briefs, June 2013, vol. 60, no. 6, pp. 326–330.  

      [2] 

      S. Chong and P.K. Chan, “A 0.9-μ/A Quiescent Current Output-Capacitorless LDO Regulator with Adaptive Power Transistors in 65-nm CMOS,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 60, no. 4, Apr. 2013, pp. 1072–1081.  

      [3] 

      X. Ming et al., “An Ultrafast Adaptively Biased Capacitorless LDO with Dynamic Charging Control,” IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 59, no. 1, Jan. 2012, pp. 40–44.  

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      S.S. Chong and P.K. Chan, “A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator with Push-Pull Composite Power Transistor,” IEEE Trans.Very Large Scale Integr. Syst., vol. 22, no. 11, Nov. 2014, pp. 2297–2306.  

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      S.W. Hong and G.H. Cho, “High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 63, no. 1, Jan. 2016, pp. 46–57.  

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      A. Maity and A. Patra, “A Hybrid-Mode Operational Transconductance Amplifier for an Adaptively Biased Low Dropout Regulator,” IEEE Trans. Power Electron., vol. 32, no. 2, Feb. 2017, pp. 1245–1254.  

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      A. Maity and A. Patra, “Tradeoffs Aware Design Procedure for an Adaptively Biased Capacitorless Low Dropout Regulator Using Nested Miller Compensation,” IEEE Trans. Power Electron., vol. 31, no. 1, Jan. 2016, pp. 369–380.  

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      R.G. Carvajal et al., “The Flipped Voltage Follower: a Useful Cell for Low-Voltage Low-Power Circuit Design,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 52, no. 7, July 2005, pp. 1276–1291.  

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      J. Ramirez-Angulo et al., “Comparison of Conventional and New Flipped Voltage Structures with Increased Input/Output Signal Swing and Current Sourcing/Sinking Capabilities,” Midwest Symp. Circuits Syst., Covington, KY, USA, Aug. 7–10, 2005, pp. 1151–1154.

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      Y. Lu et al., “A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS,” Electron. Lett., vol. 52, no. 16, Aug. 2016, pp. 1368–1370.  

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      T.Y. Man et al., “Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 55, no. 5, June 2008, pp. 1392–1401.  

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      G. Blakiewicz, “Output-Capacitorless Low-Dropout Regulator Using a Cascoded Flipped Voltage Follower,” IET Circuits, Devices Syst., vol. 5, no. 5, Sept. 2011, pp. 418–423.  

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      P. Hazucha et al., “Area-Efficient Linear Regulator with Ultra-Fast Load Regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, Apr. 2005, pp. 933–940.  

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      P.Y. Or and K.N. Leung, “An Output-Capacitorless Low-Dropout Regulator with Direct Voltage-Spike Detection,” IEEE J. Solid-State Circuits, vol. 45, no. 2, Feb. 2010, pp. 458–466.  

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      C.M. Chen, T.W. Tsai, and C.C. Hung, “Fast Transient Low-Dropout Voltage Regulator with Hybrid Dynamic Biasing Technique for SoC Application,” IEEE Trans. Very Large Scale Integr. Syst., vol. 21, no. 9, Sept. 2013, pp. 1742–1747.  

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      J. Guo et al., “Power-Area-Efficient Transient-Improved Capacitor-Free FVF-LDO with Digital Detecting Technique,” Electron. Lett., vol. 51, no. 1, Jan. 2015, pp. 8–9.  

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      J. Guo and K.N. Leung, “A 6-μW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 9, Sept. 2010, pp. 1896–1905.  

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      X.L. Tan et al., “A FVF LDO Regulator with Dual-summed Miller Frequency Compensation for Wide Load Capacitance Range Applications,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 61, no. 5, May 2014, pp. 1304–1312.  

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      Y. Lu et al., “A Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power Supply Rejection,” IEEE Trans. Circuits Syst. I: Regular Paper, vol. 62, no. 3, Mar. 2015, pp. 707–716.  

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  • Figure / Table
    • Figure / Table

      Fig. 1.

      (a) FVF cell configuration and (b) CAFVF cell.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f001.jpg
      Fig. 2.

      Example of signal evolution for ILOAD variation for internally compensated Low Dropout voltage regulator under Slew-Rate constraints.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f002.jpg
      Fig. 3.

      Structure of proposed LDO: Circuit core showing blocks that improve settling time and limit overshoot. Detailed view of implementation of amplifiers A0, A1 and A2 is also included.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f003.jpg
      Fig. 4.

      Dynamic behavior of currents (Fig. 3) when ILOAD changes in a square wave between its minimum (0.1 mA) and maximum (100 mA) with rising and falling time of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f004.jpg
      Fig. 5.

      Dynamic behavior of currents (Fig. 3) when VIN changes in a square wave between its minimum (0.9 V) and maximum (1.2 V) with rising and falling time of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f005.jpg
      Fig. 6.

      Cascode and VBIAS voltage biasing circuits.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f006.jpg
      Fig. 7.

      Small-signal model of proposed LDO.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f007.jpg
      Fig. 8.

      Simplified pole-zero map for poles and zeros below 100 MHz.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f008.jpg
      Fig. 9.

      Simulated post-layout open-loop gain of circuit in Fig. 3(a).

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f009.jpg
      Fig. 10.

      LDO layout superimposed on chip microphotograph.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f010.jpg
      Fig. 11.

      Measured line response with CL = 100 pF and ILOAD = 100 mA. (a) From 0.9 V to 1.2 V; and (b) from 1.2 V to 0.9 V with rise and fall times of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f011.jpg
      Fig. 12.

      Measured load transient response with CL = 100 pF and VIN = 0.9 V. (a) From 100 mA to 0.1 mA; and (b) from 0.1 mA to 100 mA with rise and fall times of 1 μs.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f012.jpg
      Fig. 13.

      Graphical comparison of recently published LDO regulators according to FOM proposed in [13].

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_f013.jpg
      Table 1.

      Selected values used for RC couplings.

      DeviceValueDeviceValue
      R1100 (kΩ)C21.25 (pF)
      R2335 (kΩ)C35 (pF)
      R3100 (kΩ)C40.125 (pF)
      C10.125 (kΩ)C51.25 (pF)
      Table 2.

      Multiplying factors and aspect ratios for transistors in biasing circuit.

      TransistorAspect ratio (width (μm)/length (μm))Current ratioValue
      MN1,VCN0.14/1.39M04
      MP1,VCP0.12/1.49N04
      MBN1MBN20.14/0.12N/AN/A
      MBP1MBP20.30/0.12N/AN/A
      Table 3.

      Simulated post-layout gain and phase margin values for different load conditions.

      ILOAD (mA)Gain (dB)PM (°)ILOAD (mA)Gain (dB)PM (°)
      10051.30132.0156.65115.7
      1057.24122.20.154.38107.2
      Table 4.

      Comparison of recently published LDO regulators.

      images/2017/v39n3/ETRI_J001_2017_v39n3_373_t001.jpg

      a Simulation results

      b Estimated using the maximum value of quiescent consumption