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Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators
Mohamed L. Barakat, Abhinav S. Mansingka, Ahmed G. Radwan, and Khaled N. Salama
vol. 35, no. 3, June. 2013, pp. 448-458.
http://dx.doi.org/10.4218/etrij.13.0112.0677
Keywords : Chaos, pseudorandom number generator, post-processing, FPGA.
  • Abstract
    • Abstract.

      This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32 bit implementations.
  • Authors
    • Authors

      Mohamed L. Barakat
      King Abdullah University of Science and Technology, Thuwal, Kingdom of Saudi Arabia.KAUST
      mohamed.barakat@kaust.edu.sa
      Abhinav S. Mansingka
      King Abdullah University of Science and Technology
      abhinav.mansingka@kaust.edu.sa
      Ahmed G. Radwan
      Cairo University
      ahmedgom@yahoo.com, agradwan@ieee.org
      Khaled N. Salama
      King Abdullah University of Science and Technology
      khaled.salama@kaust.edu.sa
  • References
    • References

      [1] S.Y. Hwang et al., "Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications," ETRI J., vol. 32, no. 2, Apr. 2010, pp. 222-229.
      [2] M. Asim and V. Jeoti, "Efficient and Simple Method for Designing Chaotic S-Boxes," ETRI J., vol. 30, no. 1, Feb. 2008, pp. 170-172.
      [3] M.L. Barakat, A.G. Radwan, and K.N. Salama, "Hardware Realization of Chaos-Based Block Cipher for Image Encryption," IEEE Int. Conf. Microelectron., 2011, pp. 1-5.
      [4] A. Kopp et al., "A Stochastic Differential Equation Code for Multidimensional Fokker-Planck Type Problems," Comput. Physics Commun., vol. 183, no. 3, 2012, pp. 530-542.
      [5] C.-Y. Li et al., "Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG," IEEE Trans. Very Large Scale Integ. Syst., vol. 20, no. 2, 2012, pp. 385-389.
      [6] S.-L. Chen et al., "A Fast Digital Chaotic Generator for Secure Communication," Int. J. Bifurcation Chaos, vol. 20, no. 12, 2010, pp. 3969-3987.
      [7] T. Addabbo et al., "A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 54, no. 4, 2007, pp. 816-828.
      [8] S.-L. Chen, T. Hwang, and W.-W. Lin, "Randomness Enhancement Using Digitalized Modified Logistic Map," IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 57, no. 12, 2010, pp. 996-1000.
      [9] M.A. Zidan, A.G. Radwan, and K.N. Salama, "Controllable V-Shape Multi-scroll Butterfly Attractor: System and Circuit Implementation," Int. J. Bifurcation Chaos, vol. 22, no. 6, 2012, pp. 1250143-1250156.
      [10] M.A. Zidan, A.G. Radwan, and K.N. Salama, "Random Number Generation Based on Digital Differential Chaos," Int. Midwest Symp. Circuits Syst., 2011, pp. 1-4.
      [11] T. Addabbo et al., "Pseudochaotic Lossy Compressors for True Random Number Generation," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 58, no. 8, 2011, pp. 1897-1909.
      [12] G. Taylor and G. Cox, "Digital Randomness," IEEE Spectrum, vol. 48, no. 9, 2011, pp. 32-58.
      [13] S. Li, G. Chen, and X. Mou, "On the Dynamical Degradation of Digital Piecewise Linear Chaotic Maps," Int. J. Bifurcation Chaos, vol. 15, no. 10, 2005, pp. 3119-3152.
      [14] J.V. Neumann, "Various Techniques Used in Connection With Random Digits," National Bureau of Standards Applied Mathematics Series 12, 1951, pp. 36-38.
      [15] T. Stojanovski, J. Pihl, and L. Kocarev, "Chaos-Based Random Number Generators. Part II: Practical Realization," IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 48, no. 3, 2001, pp. 382-385.
      [16] V. Fischer and M. Drutarovský, "True Random Number Generator Embedded in Reconfigurable Hardware," LNCS, Berlin-Heidelberg: Springer, 2003.
      [17] B.-J. Wang et al., "Random Number Generator of BP Neural Network Based on SHA-2 (512)," Int. Conf. Machine Learning Cybern., 2007, pp. 2708-2712.
      [18] P. Lacharme, "Analysis and Construction of Correctors," IEEE Trans. Info. Theory, vol. 55, no. 10, 2009, pp. 4742-4748.
      [19] Y.-S. Kim, J.-W. Jang, and D.-W. Lim, "Linear Corrector Overcoming Minimum Distance Limitation for Secure TRNG from (17, 9, 5) Quadratic Residue Code," ETRI J., vol. 32, no. 1, Feb. 2010, pp. 93-101.
      [20] J.C. Sprott, "A New Class of Chaotic Circuit," Physics Lett. A, vol. 266, no. 1, 2000, pp. 19-23.
      [21] T. Addabbo et al., "Low Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE Trans. CAS - Part II, vol. 53, no. 5, 2006, pp. 329-333.
      [22] T. Addabbo et al., "The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Trans. Instrum. Meas., vol. 55, no. 5, 2006, pp. 1451-1458.
      [23] J.C. Sprott, Chaos and Time-Series Analysis, Oxford, UK: Oxford University Press, 2003.
      [24] M.A. Zidan, A.G. Radwan, and K.N. Salama, "The Effect of Numerical Techniques on Differential Equation Based Chaotic Generators," IEEE Int. Conf. Microelectron. 2011, pp. 1-4.
      [25] A.S. Mansingka, A.G. Radwan, and K.N. Salama, "Design, Implementation and Analysis of Fully Digital 1-D Controllable Multiscroll Chaos," IEEE Int. Conf. Microelectron., 2011, pp. 1-5.
      [26] A.S. Mansingka et al., "Analysis of Bus Width and Delay on a Fully Digital Signum Nonlinearity Chaotic Oscillator," Int. Midwest Symp. Circuits Syst., 2011, pp. 1-4.
      [27] R. Devaney, An Introduction to Chaotic Dynamical System, 2nd ed., Boulder, CO: Westview Press, 2003.
      [28] S. Kodba, M. Perc, and M. Marhl, "Detecting Chaos from a Time Series," European J. Physics, vol. 26, no. 1, 2005, pp. 205-215.
      [29] M.E. Yalcin, J.A.K. Suykens, and J. Vandewalle, "True Random Bit Generation from a Double-Scroll Attractor," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, no. 7, 2004, pp. 1395-1404.
      [30] R.B. Davies, "Exclusive OR (XOR) and Hardware Random Number Generators," 2002. http://www.robertnz.net/pdf/xor2.pdf
      [31] T. Addabbo et al., Digitized Chaos for Pseudo-random Number Generation in Cryptography, Series: Studies on Computational Intelligence, Vol. 354, L. Kocarev and S. Lian, Eds., Springer, 2011.
      [32] A. Rukhin et al., "A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications," NIST Special Publication 800-22, 2001.
      [33] H. Kim et al., "Efficient Masking Methods Appropriate for the Block Ciphers ARIA and AES," ETRI J., vol. 32, no. 3, June 2010, pp. 370-379.
      [34] E. Lorenz, "Deterministic Nonperiodic Flow," J. Atmospheric Sci., vol. 20, no. 2, 1963, pp. 130-141.
      [35] G.R. Chen and J.H. Lu, Dynamics of the Lorenz System Family: Analysis, Control and Synchronization, Beijing: Sci. Press, 2003.
      [36] A. Elwakil and M. Kennedy, "Construction of Classes of Circuit Independent Chaotic Oscillators Using Passive-Only Nonlinear Devices," IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 48, no. 3, 2001, pp. 289-307.
      [37] C.-Y. Li, T.-Y. Chang, and C.-C. Huang, "A Nonlinear PRNG Using Digitized Logistic Map with Self-Reseeding Method," Int. Symp. VLSI Design Autom. Test (VLSI-DAT), 2010, pp. 108-111.
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