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An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder
Kibum Suh, Seongmo Park, and Hanjin Cho
Abstract :	In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quanti-zation/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.
Key word :	Intra prediction, integer transform, quantization, inverse integer transform, inverse quantization, H.264.
DOI :	http://dx.doi.org/10.4218/etrij.05.0905.0032
Cite this :	Kibum Suh, Seongmo Park, and Hanjin Cho, "An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder," ETRI Journal, vol. 27, no. 5, Oct. 2005, pp. 511-524. http://dx.doi.org/10.4218/etrij.05.0905.0032
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