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An Efficient Built-In Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories
Dong -Chual Kang, Sung Min Park, and Sang-Bock Cho
Abstract :	As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.
Key word :	Memory, BIST, NBLSF, NPSF, testing.
DOI :	http://dx.doi.org/10.4218/etrij.04.0804.0007
Cite this :	Dong -Chual Kang, Sung Min Park, and Sang-Bock Cho, "An Efficient Built-In Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories," ETRI Journal, vol. 26, no. 6, Dec. 2004, pp. 520-534. http://dx.doi.org/10.4218/etrij.04.0804.0007
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